Full Subtractor using Two Half Subtractors

Dataflow — Half Subtractor

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 
-- Design Name: 
-- Module Name:    HALF_SUBTRACTOR_MODULE - Dataflow 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: Half Subtractor
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity HALF_SUBTRACTOR_MODULE is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           DIFF : out  STD_LOGIC;
           BORROW : out  STD_LOGIC);
end HALF_SUBTRACTOR_MODULE;

architecture Dataflow of HALF_SUBTRACTOR_MODULE is

begin
    DIFF   <= A xor B;
    BORROW <= (not A) and B;

end Dataflow;

Dataflow — Full Subtractor Using Half Subtractors

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 
-- Design Name: 
-- Module Name:    FULL_SUBTRACTOR_MODULE - Dataflow 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: Full Subtractor using Two Half Subtractors
--
-- Dependencies: HALF_SUBTRACTOR_MODULE
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FULL_SUBTRACTOR_MODULE is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           BIN : in STD_LOGIC;
           DIFF : out  STD_LOGIC;
           BORROW : out  STD_LOGIC);
end FULL_SUBTRACTOR_MODULE;

architecture Dataflow of FULL_SUBTRACTOR_MODULE is

    signal D1, B1, B2 : STD_LOGIC;

begin

    -- First Half Subtractor
    D1 <= A xor B;
    B1 <= (not A) and B;

    -- Second Half Subtractor
    DIFF <= D1 xor BIN;
    B2   <= (not D1) and BIN;

    -- Final Borrow
    BORROW <= B1 or B2;

end Dataflow;

Testbench

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-- Testbench for Full Subtractor
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TB_FULL_SUBTRACTOR is
end TB_FULL_SUBTRACTOR;

architecture behavior of TB_FULL_SUBTRACTOR is

    signal A, B, BIN : STD_LOGIC;
    signal DIFF, BORROW : STD_LOGIC;

begin

    uut: entity work.FULL_SUBTRACTOR_MODULE
        port map (
            A => A,
            B => B,
            BIN => BIN,
            DIFF => DIFF,
            BORROW => BORROW
        );

    process
    begin
        A <= '0'; B <= '0'; BIN <= '0'; wait for 10 ns;
        A <= '0'; B <= '0'; BIN <= '1'; wait for 10 ns;
        A <= '0'; B <= '1'; BIN <= '0'; wait for 10 ns;
        A <= '0'; B <= '1'; BIN <= '1'; wait for 10 ns;
        A <= '1'; B <= '0'; BIN <= '0'; wait for 10 ns;
        A <= '1'; B <= '0'; BIN <= '1'; wait for 10 ns;
        A <= '1'; B <= '1'; BIN <= '0'; wait for 10 ns;
        A <= '1'; B <= '1'; BIN <= '1'; wait for 10 ns;

        wait;
    end process;

end behavior;