Full Subtractor using Two Half Subtractors

Dataflow — Half Subtractor

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 
-- Design Name: 
-- Module Name:    HALF_SUBTRACTOR_MODULE - Dataflow 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: Half Subtractor
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity HALF_SUBTRACTOR_MODULE is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           DIFF : out  STD_LOGIC;
           BORROW : out  STD_LOGIC);
end HALF_SUBTRACTOR_MODULE;

architecture Dataflow of HALF_SUBTRACTOR_MODULE is

begin
    DIFF   <= A xor B;
    BORROW <= (not A) and B;

end Dataflow;

Dataflow — Full Subtractor Using Half Subtractors

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:00:57 07/13/2026 
-- Design Name: 
-- Module Name:    FULL_SUBTRACTOR_MODULE - Dataflow 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FULL_SUBTRACTOR_MODULE is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           BIN : in  STD_LOGIC;
           DIFF : out  STD_LOGIC;
           BORROW : out  STD_LOGIC);
end FULL_SUBTRACTOR_MODULE;

architecture Dataflow of FULL_SUBTRACTOR_MODULE is

component HALF_SUBTRACTOR_MODULE
	Port ( A : in STD_LOGIC;
			 B : in  STD_LOGIC;
			 DIFF : out STD_LOGIC;
			 BORROW : out STD_LOGIC);
end component;

signal D1, B1, B2 : STD_LOGIC;

begin

    -- First Half Subtractor
    HS1 : HALF_SUBTRACTOR_MODULE
        port map(
            A => A,
            B => B,
            DIFF => D1,
            BORROW => B1
        );

    -- Second Half Subtractor
    HS2 : HALF_SUBTRACTOR_MODULE
        port map(
            A => D1,
            B => BIN,
            DIFF => DIFF,
            BORROW => B2
        );

    -- Final Borrow
    BORROW <= B1 or B2;

end Dataflow;

Testbench

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   10:35:01 07/13/2026
-- Design Name:   
-- Module Name:   /home/student/Desktop/13000224121/FULL_SUBTRACTOR_USING_HALF_SUBTRACTOR_PROJECT/TB_FULL_SUBTRACTOR.vhd
-- Project Name:  FULL_SUBTRACTOR_USING_HALF_SUBTRACTOR_PROJECT
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: FULL_SUBTRACTOR_MODULE
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY TB_FULL_SUBTRACTOR IS
END TB_FULL_SUBTRACTOR;
 
ARCHITECTURE behavior OF TB_FULL_SUBTRACTOR IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT FULL_SUBTRACTOR_MODULE
    PORT(
         A : IN  std_logic;
         B : IN  std_logic;
         BIN : IN  std_logic;
         DIFF : OUT  std_logic;
         BORROW : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal A : std_logic := '0';
   signal B : std_logic := '0';
   signal BIN : std_logic := '0';

 	--Outputs
   signal DIFF : std_logic;
   signal BORROW : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
--   constant <clock>_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: FULL_SUBTRACTOR_MODULE PORT MAP (
          A => A,
          B => B,
          BIN => BIN,
          DIFF => DIFF,
          BORROW => BORROW
        );

   -- Clock process definitions
--   <clock>_process :process
--   begin
--		<clock> <= '0';
--		wait for <clock>_period/2;
--		<clock> <= '1';
--		wait for <clock>_period/2;
--   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		  A <= '0'; B <= '0'; BIN <= '0'; wait for 10 ns;
      A <= '0'; B <= '0'; BIN <= '1'; wait for 10 ns;
      A <= '0'; B <= '1'; BIN <= '0'; wait for 10 ns;
      A <= '0'; B <= '1'; BIN <= '1'; wait for 10 ns;
      A <= '1'; B <= '0'; BIN <= '0'; wait for 10 ns;
      A <= '1'; B <= '0'; BIN <= '1'; wait for 10 ns;
      A <= '1'; B <= '1'; BIN <= '0'; wait for 10 ns;
      A <= '1'; B <= '1'; BIN <= '1'; wait for 10 ns;

      -- insert stimulus here 

      wait;
   end process;

END;