Full Adder

Dataflow

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:33:41 04/13/2026 
-- Design Name: 
-- Module Name:    FULL_ADDER_MODULE - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FULL_ADDER_MODULE is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           Cin : in  STD_LOGIC;
           Sum : out  STD_LOGIC;
           Cout : out  STD_LOGIC);
end FULL_ADDER_MODULE;

architecture Dataflow of FULL_ADDER_MODULE is

begin
	Sum <= A xor B xor Cin;
	Cout <= (A and B) or (B and Cin) or (A and Cin);

end Dataflow;

Testbench

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   17:39:13 04/13/2026
-- Design Name:   
-- Module Name:   /home/student/Desktop/13000224121/FULL_ADDER_PROJECT/full_adder_tb.vhd
-- Project Name:  FULL_ADDER_PROJECT
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: FULL_ADDER_MODULE
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY full_adder_tb IS
END full_adder_tb;
 
ARCHITECTURE behavior OF full_adder_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT FULL_ADDER_MODULE
    PORT(
         A : IN  std_logic;
         B : IN  std_logic;
         Cin : IN  std_logic;
         Sum : OUT  std_logic;
         Cout : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal A : std_logic := '0';
   signal B : std_logic := '0';
   signal Cin : std_logic := '0';

 	--Outputs
   signal Sum : std_logic;
   signal Cout : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
--   constant <clock>_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: FULL_ADDER_MODULE PORT MAP (
          A => A,
          B => B,
          Cin => Cin,
          Sum => Sum,
          Cout => Cout
        );

   -- Clock process definitions
--   <clock>_process :process
--   begin
--		<clock> <= '0';
--		wait for <clock>_period/2;
--		<clock> <= '1';
--		wait for <clock>_period/2;
--   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		A <= '0'; B <= '0'; Cin <= '0'; Wait for 100 ns;
		A <= '0'; B <= '0'; Cin <= '1'; Wait for 100 ns;
		A <= '0'; B <= '1'; Cin <= '0'; Wait for 100 ns;
		A <= '0'; B <= '1'; Cin <= '1'; Wait for 100 ns;
		A <= '1'; B <= '0'; Cin <= '0'; Wait for 100 ns;
		A <= '1'; B <= '0'; Cin <= '1'; Wait for 100 ns;
		A <= '1'; B <= '1'; Cin <= '0'; Wait for 100 ns;
		A <= '1'; B <= '1'; Cin <= '1'; Wait for 100 ns;



      wait;
   end process;

END;