F1=A’B+AC+BC’

Dataflow

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:13:24 04/06/2026 
-- Design Name: 
-- Module Name:    F1_MODULE - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity F1_MODULE is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C : in  STD_LOGIC;
           F1 : out  STD_LOGIC);
end F1_MODULE;

architecture Dataflow of F1_MODULE is

begin
	F1 <= ((not A) and B) or (A and C) or (B and (not C));

end Dataflow;

Testbench

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   19:21:54 04/06/2026
-- Design Name:   
-- Module Name:   /home/student/Desktop/13000224121/F1/tb.vhd
-- Project Name:  F1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: F1_MODULE
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tb IS
END tb;
 
ARCHITECTURE behavior OF tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT F1_MODULE
    PORT(
         A : IN  std_logic;
         B : IN  std_logic;
         C : IN  std_logic;
         F1 : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal A : std_logic := '0';
   signal B : std_logic := '0';
   signal C : std_logic := '0';

 	--Outputs
   signal F1 : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: F1_MODULE PORT MAP (
          A => A,
          B => B,
          C => C,
          F1 => F1
        );
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		A <= '0'; B <= '0'; C <= '0'; Wait for 100 ns;
		A <= '0'; B <= '0'; C <= '1'; Wait for 100 ns;
		A <= '0'; B <= '1'; C <= '0'; Wait for 100 ns;
		A <= '0'; B <= '1'; C <= '1'; Wait for 100 ns;
		A <= '1'; B <= '0'; C <= '0'; Wait for 100 ns;
		A <= '1'; B <= '0'; C <= '1'; Wait for 100 ns;
		A <= '1'; B <= '1'; C <= '0'; Wait for 100 ns;
		A <= '1'; B <= '1'; C <= '1'; Wait for 100 ns;

      wait;
   end process;

END;