Adder subtractor composite unit
Dataflow — XOR Gate
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-- Company:
-- Engineer:
--
-- Create Date: 10:54:53 07/13/2026
-- Design Name:
-- Module Name: XOR_GATE_MODULE - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity XOR_GATE_MODULE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end XOR_GATE_MODULE;
architecture Dataflow of XOR_GATE_MODULE is
begin
Y <= A xor B;
end Dataflow;
Dataflow — Full Adder
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-- Company:
-- Engineer:
--
-- Create Date: 10:57:35 07/13/2026
-- Design Name:
-- Module Name: FA_MODULE - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FA_MODULE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
SUM : out STD_LOGIC;
CARRY : out STD_LOGIC);
end FA_MODULE;
architecture Dataflow of FA_MODULE is
begin
SUM <= A xor B xor Cin;
CARRY <= (A and B) or (B and Cin) or (A and Cin);
end Dataflow;
Dataflow — ADDSUB
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:02:44 07/13/2026
-- Design Name:
-- Module Name: ADDSUB - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ADDSUB is
Port ( A : in STD_LOGIC_VECTOR(3 DOWNTO 0);
B : in STD_LOGIC_VECTOR(3 DOWNTO 0);
M : in STD_LOGIC;
S : out STD_LOGIC_VECTOR(3 DOWNTO 0);
C : out STD_LOGIC);
end ADDSUB;
architecture Dataflow of ADDSUB is
component XOR_GATE_MODULE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end component;
component FA_MODULE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
SUM : out STD_LOGIC;
CARRY : out STD_LOGIC);
end component;
signal sum : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal cout : STD_LOGIC_VECTOR (4 DOWNTO 0);
begin
cout (0) <= M;
L1 : for i in 3 DOWNTO 0 generate
X1 : XOR_GATE_MODULE port map (B(i), M, sum(i));
end generate;
l2: for i in 3 DOWNTO 0 generate
FA1: FA_MODULE port map (A(i), sum(i), cout(i), s(i), cout(i+1));
end generate;
C <= cout(4);
end Dataflow;
Testbench — M = ‘0’
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:29:15 07/13/2026
-- Design Name:
-- Module Name: /home/student/Desktop/13000224121/ADDER_SUBTRACTOR_COMPOSITE_UNIT/ADD_SUB_TB.vhd
-- Project Name: ADDER_SUBTRACTOR_COMPOSITE_UNIT
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ADDSUB
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ADD_SUB_TB IS
END ADD_SUB_TB;
ARCHITECTURE behavior OF ADD_SUB_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ADDSUB
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
M : IN std_logic;
S : OUT std_logic_vector(3 downto 0);
C : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal M : std_logic := '0';
--Outputs
signal S : std_logic_vector(3 downto 0);
signal C : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ADDSUB PORT MAP (
A => A,
B => B,
M => M,
S => S,
C => C
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A(0) <= '0'; B(0) <= '0'; Wait for 100 ns;
A(1) <= '0'; B(1) <= '1'; Wait for 100 ns;
A(2) <= '1'; B(2) <= '0'; Wait for 100 ns;
A(3) <= '1'; B(3) <= '1'; Wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
Testbench — M = ‘1’
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:37:52 07/13/2026
-- Design Name:
-- Module Name: /home/student/Desktop/13000224121/ADDER_SUBTRACTOR_COMPOSITE_UNIT/TB_Addsub.vhd
-- Project Name: ADDER_SUBTRACTOR_COMPOSITE_UNIT
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ADDSUB
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_Addsub IS
END TB_Addsub;
ARCHITECTURE behavior OF TB_Addsub IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ADDSUB
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
M : IN std_logic;
S : OUT std_logic_vector(3 downto 0);
C : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal M : std_logic := '1';
--Outputs
signal S : std_logic_vector(3 downto 0);
signal C : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ADDSUB PORT MAP (
A => A,
B => B,
M => M,
S => S,
C => C
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A(0) <= '0'; B(0) <= '0'; Wait for 100 ns;
A(1) <= '0'; B(1) <= '1'; Wait for 100 ns;
A(2) <= '1'; B(2) <= '0'; Wait for 100 ns;
A(3) <= '1'; B(3) <= '1'; Wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;