4:1 MUX Circuit

Dataflow

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:53:57 07/13/2026 
-- Design Name: 
-- Module Name:    MUX_4_1_MODULE - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MUX_4_1_MODULE is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C : in  STD_LOGIC;
           D : in  STD_LOGIC;
           S0 : in  STD_LOGIC;
           S1 : in  STD_LOGIC;
           Z : out  STD_LOGIC);
end MUX_4_1_MODULE;

architecture Behavioral of MUX_4_1_MODULE is

begin
process (A,B,C,D,S0,S1) is
begin
	if (S0 = '0' and S1 = '0') then
	Z <= A;
	
	elsif (S0 = '1' and S1 = '0') then
	Z <= C;
	
	elsif (S0 = '0' and S1 = '1') then
	Z <= B;
	
	else
	Z <= D;
	
	end if;
end process;

end Behavioral;

Testbench

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   11:58:23 07/13/2026
-- Design Name:   
-- Module Name:   /home/student/Desktop/13000224121/MUX_4_1/MUX_4_1_Tb.vhd
-- Project Name:  MUX_4_1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: MUX_4_1_MODULE
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY MUX_4_1_Tb IS
END MUX_4_1_Tb;
 
ARCHITECTURE behavior OF MUX_4_1_Tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT MUX_4_1_MODULE
    PORT(
         A : IN  std_logic;
         B : IN  std_logic;
         C : IN  std_logic;
         D : IN  std_logic;
         S0 : IN  std_logic;
         S1 : IN  std_logic;
         Z : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal A : std_logic := '0';
   signal B : std_logic := '0';
   signal C : std_logic := '0';
   signal D : std_logic := '0';
   signal S0 : std_logic := '0';
   signal S1 : std_logic := '0';

 	--Outputs
   signal Z : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
--   constant <clock>_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: MUX_4_1_MODULE PORT MAP (
          A => A,
          B => B,
          C => C,
          D => D,
          S0 => S0,
          S1 => S1,
          Z => Z
        );

   -- Clock process definitions
--   <clock>_process :process
--   begin
--		<clock> <= '0';
--		wait for <clock>_period/2;
--		<clock> <= '1';
--		wait for <clock>_period/2;
--   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		A <= '1'; B <= '0'; C <= '1'; D <= '0';
		S0 <= '0'; S1 <= '0'; Wait for 100 ns;
		S0 <= '0'; S1 <= '1'; Wait for 100 ns;
		S0 <= '1'; S1 <= '0'; Wait for 100 ns;
		S0 <= '1'; S1 <= '1'; Wait for 100 ns;
      

      -- insert stimulus here 

      wait;
   end process;

END;