1:8 DEMUX Circuit

Dataflow

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:52:56 07/13/2026 
-- Design Name: 
-- Module Name:    DEMUX_1_8_MODULE - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DEMUX_1_8_MODULE is
    Port ( din : in  STD_LOGIC;
           s : in  STD_LOGIC_VECTOR(2 downto 0);
           dout : out  STD_LOGIC_VECTOR(7 downto 0));
end DEMUX_1_8_MODULE;

architecture Behavioral of DEMUX_1_8_MODULE is

begin
process (din, s)
begin
	dout <= (others => '0');
	if din = '1' then
	case s is 
		when "000" => dout(0) <= '1';
		when "001" => dout(1) <= '1';
		when "010" => dout(2) <= '1';
		when "011" => dout(3) <= '1';
		when "100" => dout(4) <= '1';
		when "101" => dout(5) <= '1';
		when "110" => dout(6) <= '1';
		when "111" => dout(7) <= '1';
		when others => dout <= (others => '0');
		end case;
	end if;
end process;

end Behavioral;

Testbench

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:59:46 07/13/2026
-- Design Name:   
-- Module Name:   /home/student/Desktop/13000224121/DEMUX_1_8/DEMUX_1_8_TB.vhd
-- Project Name:  DEMUX_1_8
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: DEMUX_1_8_MODULE
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values

 
ENTITY DEMUX_1_8_TB IS
END DEMUX_1_8_TB;
 
ARCHITECTURE behavior OF DEMUX_1_8_TB IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT DEMUX_1_8_MODULE
    PORT(
         din : IN  std_logic;
         s : IN  std_logic_vector(2 downto 0);
         dout : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal din : std_logic := '0';
   signal s : std_logic_vector(2 downto 0) := (others => '0');

 	--Outputs
   signal dout : std_logic_vector(7 downto 0);
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
--   constant <clock>_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: DEMUX_1_8_MODULE PORT MAP (
          din => din,
          s => s,
          dout => dout
        );

   -- Clock process definitions
--   <clock>_process :process
--   begin
--		<clock> <= '0';
--		wait for <clock>_period/2;
--		<clock> <= '1';
--		wait for <clock>_period/2;
--   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		din <= '1';
		for i in 0 to 7 loop
			s <= std_logic_vector(to_unsigned (i, 3));
			wait for 100 ns;
		end loop;
		
		din <= '0';
		for i in 0 to 7 loop
			s <= std_logic_vector(to_unsigned (i, 3));
			wait for 100 ns;
		end loop;

      -- insert stimulus here 

      wait;
   end process;

END;